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19-1635; Rev 1; 10/00
KIT ATION EVALU E AILABL AV
Complete Dual-Band Quadrature Transmitters
General Description Features
o Dual-Band, Triple-Mode Operation o +7dBm Output Power with -54dBc ACPR o 100dB Power Control Range o Supply Current Drops as Output Power Is Reduced o Dual Synthesizer for IF and RF LO o Dual On-Chip IF VCO o QSPI/SPI/MICROWIRE-Compatible 3-Wire Bus o Digitally Controlled Operational Modes o +2.7V to +5.5V Operation o Single Sideband Upconverter Eliminates SAW Filters
MAX2360/MAX2362/MAX2364
The MAX2360 dual-band, triple-mode complete transmitter for cellular phones represents the most integrated and architecturally advanced solution to date for this application. The device takes a differential I/Q baseband input and mixes it up to IF through a quadrature modulator and IF variable-gain amplifier (VGA). The signal is then routed to an external bandpass filter and upconverted to RF through an SSB mixer and RF VGA. The signal is further amplified with an on-board PA driver. Dual IF synthesizers, dual RF synthesizers, a local oscillator (LO) buffer, and a 3-wire programmable bus complete the basic functional blocks of this IC. The MAX2362 supports singleband, single-mode (PCS) operation. The MAX2364 supports single-band cellular dual-mode operation. The MAX2360 enables architectural flexibility because its two IF voltage-controlled oscillators (VCOs), two IF ports, two RF LO input ports, and three PA driver output ports allow the use of a single receive IF frequency and split-band PCS filters for optimum out-of-band noise performance. The PA drivers allow up to three RF SAW filters to be eliminated. Select a mode of operation by loading data on the SPITM/QSPITM/MICROWIRETM-compatible 3-wire serial bus. Charge-pump current, sideband rejection, IF/RF gain balancing, standby, and shutdown are also controlled with the serial interface. The MAX2360/MAX2362/MAX2364 come in a 48-pin TQFP-EP package and are specified for the extended (-40C to +85C) temperature range.
Ordering Information
PART MAX2360ECM MAX2362ECM MAX2364ECM *Exposed paddle TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 48 TQFP-EP* 48 TQFP-EP* 48 TQFP-EP*
Functional Diagram
LOH RFPLL VCC
43 42 41
Triple-Mode, Dual-Mode, or Single-Mode Mobile Phones Satellite Phones Wireless Data Links (WAN/LAN) Wireless Local Area Networks (LANs) High-Speed Data Modems High-Speed Digital Cordless Phones Wireless Local Loop (WLL)
Pin Configurations appear at end of data sheet. Selector Guide appears at end of data sheet.
RFL RFH0 LOCK VCC IDLE VCC TXGATE IFINL+ IFINLIFINH+ IFINHRBIAS
1 2 3 4 5 6 7 8 9 10 11 12
48
47
46
45
44
40
39
38
RFPLL IFPLL
37
RFCP VCC IFCP VCC
GND RFH1
Applications
GND GND LOL
36 35 34 33 32 31
MAX2360
90 0 +45 -45 /2
30 29 28
0
90
/2
27 26 25
REF N.C. N.C. TANKH+ TANKHTANKL+ TANKLIFLO VCC SHDN II+
13
14
15
16
17
18
19
20
21
22
23
CS IFOUTHIFOUTH+
IFOUTL+ IFOUTLVGC
CLK DI
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
VCC
VCC Q+ Q-
24
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +3.6V RFL, RFH0, RFH1................................................................+5.5V DI, CLK, CS, VGC, SHDN, TXGATE, IDLE, LOCK ................................................-0.3V to (VCC + 0.3V) AC Input Pins (IFINL, IFINH, Q, I, TANKL, TANKH, REF, RFPLL, LOL, LOH)..........................................1.0V peak Digital Input Current (SHDN, TXGATE, IDLE, CLK, DI, CS) ................................................................10mA Continuous Power Dissipation (TA = +70C) 48-Pin TQFP-EP (derate 27mW/C above +70C)...........2.16W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(MAX2360/2/4 test fixture: VCC = VBATT = 2.75V, SHDN = IDLE = TXGATE = 2.0V, VGC = 2.5V, RBIAS = 16k, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, and operating modes are defined in Table 6.) PARAMETER Operating Supply Voltage VGC = 0.5V PCS mode VGC = 2.0V VGC = 2.5V VGC = 0.5V (Note 1) Operating Supply Current Cellular digital mode VGC = 2.0V VGC = 2.5V VGC = 0.5V FM mode VGC = 2.0V VGC = 2.5V Addition for IFLO buffer IDLE = 0.6V, cell idle STBY = 0.6V, TXGATE = 0.6V Logic High Logic Low Logic Input Current VGC Input Current VGC Input Resistance During Shutdown Lock Indicator High Lock Indicator Low (Note 6) (Note 6) (Note 6) (Note 6) SHDN = 0.6V (Note 6) 50k pull-up load (Note 6) 50k pull-up load (Note 6) -5 -10 225 VCC - 0.4 0.4 280 RFPLL off 2.0 0.6 +5 +10 CONDITIONS MIN 2.7 92 97 132 91 95 132 85 89 114 6.5 15 26 11 0.5 20 A V V A A k V V TYP MAX 3.0 118 123 161 110 122 164 110 114 142 9.5 20 34 mA UNITS V
SHDN = 0.6V, sleep mode
2
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Complete Dual-Band Quadrature Transmitters
ELECTRICAL CHARACTERISTICS
(MAX2360/62/64 evaluation kit, 50 system, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differential, common mode = VCC/2, 300kHz quadrature CW tones, RF and IF synthesizers locked with passive lead-lag second-order loop filter, REF = 200mVp-p at 19.68MHz, VCC = SHDN = IDLE = CS = TXGATE = 2.75V, VBAT = 2.75V, IF output load = 400, LOH, LOL input power = -7dBm, fLOL = 966MHz, fLOH = 1750MHz, IFINH = 125mVRMS at 130MHz, IS-95 CDMA modulation fRFH0 = fRFH1 = 1880MHz, fRFL = 836MHz, TA = +25C, unless otherwise noted.) PARAMETER IF_BAND = low IF_BAND = high VCC = 2.7V to 3.0V (Notes 2, 3, 6) VGC = 0.5V to 2.5V, IFG = 100 VGC = 2.5V, IFG = 100, ACPR = -70dBc Relative to +25C, TA = -40C to +85C (Note 4) VGC = 2.5V, IFG = 100 VGC = 2.5V, IFG = 100 VGC = 0.5V to 2.5V, IFG = 100 VGC = 2.5V, IFG = 111, I/Q modulation VGC = 2.5V, IFG = 111, direct VCO modulation IF_BAND = low IF_BAND = high RFL port RFH0 and RFH1 ports -1 30 30 49 38 85 -8.5 -5.5 1.35 CONDITIONS MIN TYP 120-235 120-300 VCC/2 85 -10 +1 VCC 1.25 MAX UNITS MODULATOR, QUADRATURE MODES (CDMA, PCS, FM_IQ) IF Frequency Range I/Q Common-Mode Input Voltage IF Gain Control Range IF Output Power at IFOUTL and IFOUTH, CDMA Mode Gain Variation Over Temperature Carrier Suppression Sideband Suppression MODULATOR, FM MODE IF Gain Control Range Output Power at IFOUTL Output Power at IFOUTL UPCONVERTER AND PREDRIVER IF Frequency Range RFL Frequency Range RFH Frequency Range LOL Frequency Range LOH Frequency Range RFPLL Frequency Range Output Power, RFL Port Output Power, RFH1 Port Output Power, RFH0 Port Power Control Range Gain Variation Over Temperature LO Leakage Image Signal 120-200 180-300 800-1000 1700-2000 800-1150 1400-2300 1300 2300 7 12 7.5 6.6 30 1 -17 -29 2 MHz MHz MHz MHz MHz MHz dBm dBm dBm dB dB dBm dBc MHz V dB dBm dB dB dB dB dBm dBm
MAX2360/MAX2362/MAX2364
Cellular frequency operation PCS frequency operation VGC = 2.5V ACPR = -54dBc FM mode
VGC = 2.6V, ACPR = -54dBc VGC = 2.6V, ACPR = -54dBc VGC = 0.5V to 2.5V Relative to +25C, TA = -40C to +85C (Note 4)
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3
Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
ELECTRICAL CHARACTERISTICS (continued)
(MAX2360/62/64 evaluation kit, 50 system, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differential, common mode = VCC/2, 300kHz quadrature CW tones, RF and IF synthesizers locked with passive lead-lag second-order loop filter, REF = 200mVp-p at 19.68MHz, VCC = SHDN = IDLE = CS = TXGATE = 2.75V, VBAT = 2.75V, IF output load = 400, LOH, LOL input power = -7dBm, fLOL = 966MHz, fLOH = 1750MHz, IFINH = 125mVRMS at 130MHz, IS-95 CDMA modulation fRFH0 = fRFH1 = 1880MHz, fRFL = 836MHz, TA = +25C, unless otherwise noted.) PARAMETER IF_PLL Reference Frequency Frequency Reference Signal Level IF Main Divide Ratio IF Reference Divider Ratio VCO Operating Range IF LO Output Power VCO = low VCO = high BUF_EN = 1 ICP = 00 (Note 6) Charge-Pump Source/Sink Current ICP = 01 (Note 6) ICP = 10 (Note 6) ICP = 11 (Note 6) Turbolock Boost Current Charge-Pump Source/Sink Matching Charge-Pump High-Z Leakage RF_PLL RF Main Divide Ratio RF Reference Divide Ratio Maximum Phase-Detector Comparison Frequency RCP = 00 (Note 6) Charge-Pump Source/Sink Current RCP = 01 (Note 6) RCP = 10 (Note 6) RCP = 11 (Note 6) Turbolock Boost Current Charge-Pump Source/Sink Matching Charge-Pump High-Z Leakage RFPLL Input Sensitivity Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: (Notes 5, 6) Locked, all values of RCP, over specified compliance range (Note 6) Over specified compliance range 160 100 135 210 270 245 (Notes 5, 6) Locked, all values of ICP, over specified compliance range (Note 6) Over specified compliance range 4096 2 10 165 230 340 450 435 5 10 225 310 460 630 630 A % nA mVp-p A 115 145 235 300 265 5 0.1 256 2 240-470 240-600 -6 175 235 350 465 450 5 10 262144 8192 MHz 230 315 470 625 615 A % nA A 30 0.6 16384 2048 MHz dBm MHz Vp-p CONDITIONS MIN TYP MAX UNITS
See Table 6 for register settings. ACPR is met over the specified VCM range. VCM must be supplied by the I/Q baseband source with 6A capability. Guaranteed by design and characterization. When enabled, turbolock is active during acquisition and injects boost current in addition to the normal charge-pump current. >25C guaranteed by production test, <25C guaranteed by design and characterization.
4
_______________________________________________________________________________________
Complete Dual-Band Quadrature Transmitters
Typical Operating Characteristics
(MAX2360EVKIT, VCC = +2.75V, TA = +25C, unless otherwise noted.)
IF VCO VOLTAGE vs. TIME
MAX2360/2/4-01
MAX2360/2/4-02
MAX2360/MAX2362/MAX2364
TANK 1/S11 vs. FREQUENCY
20 10 POUT (dBm), ACPR/ALTR (dBc) 0 -10 -20 -30 -40 -50 -60 -70
OUTPUT POWER, ACPR, ICC vs. VGC
MAX2360/2/4-03
CELLULAR CDMA, RFL
200 182
LOCK
5 4 3 2 1 z0 = 200
POUT
164 146 ICC (mA) 128 ICC ADJACENT 110 92 74 56
VOLTS (1V/div)
CS
ALTERNATE 1.5 1.7 1.9 2.1 VGC (V) 2.3 2.5 2.7
38 20
TIME (200s/div)
EQUIVALENT PARALLEL R-C 1: 200MHz, 1.76k, 0.26pF 2: 260MHz, 1.66k, 0.31pF
3: 330MHz, 1.58k, 0.34pF 4: 780MHz, 1.21k, 0.43pF 5: 1GHz, 0.94k, 0.47pF
-80
OUTPUT POWER, ACPR, ICC vs. VGC
10 0 POUT (dBm), ACPR/ALTR (dBc) -10 -20 -30 -40 -50 -60 -70 ALTERNATE -80 1.5 1.7 1.9 2.1 VGC (V) 2.3 2.5 2.7 ADJACENT ICC POUT
MAX2360/2/4-04
OUTPUT POWER, ACPR, ICC TOTAL vs. VGC
200 180 POUT (dBm), ACPR/ALTR (dBc) 160 ICC TOTAL (mA) 140 120 100 80 60 40 20 10 0 -10 -20 -30 -40 ADJACENT -50 ALTERNATE -60 -70 -80 1.5 1.7 1.9 2.1 VGC (V) 2.3 2.5 2.7 60 40 20 -120 0 -100 80 ICC POUT
MAX2360/2/4-05
IF OUTPUT POWER vs. VGC AND IF DAC SETTING
180 160 ICC TOTAL (mA) POUT (dBm) 140 120 100 -40 -60 -80 111 101 001 010 011 0.5 1.0 1.5 VGC (V) 2.0 2.5 3.0 110 100
MAX2360/2/4-06
PCS CDMA, RFH0
PCS CDMA, RFH1
200
0 -20
000
IF OUTPUT POWER vs. VGC
MAX2360/2/4-07
IF OUTPUT POWER vs. VGC
MAX2360/2/4-08
SIDEBAND SUPPRESSION AND LO FEEDTHROUGH (IFOUTH)
-10 -20 -30 POUT (dBm) -40 -50 -60 -70 -80 -90 SIDEBAND LO DESIRED
MAX2360/2/4-09
0 -10 -20 -30 IF POWER (dBm) -40 -50 -60 -70 -80 -90 -100 -110 0 0.5 1.0 1.5 +25C
0 -20 2.7V, 3.0V, 3.3V -40 POUT (dBm) -60 -80 -100 -120
0
-40C
+85C
-100 0 0.5 1.0 1.5 VGC (V) 2.0 2.5 3.0 129.98 130.18 130.38 130.58 130.78 FREQUENCY (MHz)
2.0
2.5
3.0
VGC (V)
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5
Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
Typical Operating Characteristics (continued)
(MAX2360EVKIT, VCC = +2.75V, TA = +25C, unless otherwise noted.)
IFOUTH DIFFERENTIAL PORT OUTPUT IMPEDANCE
MAX2360/2/4-10
I/Q BASEBAND FREQUENCY RESPONSE
0 -0.5 -1.0 (dBc) -1.5 -2.0 -2.5 -3.0 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) 800 700 PARALLEL RESISTANCE () 600 500 400 300 200 100 0
IFINH DIFFERENTIAL PORT INPUT IMPEDANCE
4.0 3.5 PARALLEL CAPACITANCE (pF) 3.0 PARALLEL RESISTANCE () 600 500 400 300 200 CAPACITANCE 100 0 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz) 1 0 RESISTANCE
MAX2360/2/4-12
MAX2360/2/4-11
6 5 4 3 2
RESISTANCE
2.5 2.0 1.5
CAPACITANCE
1.0 0.5 0
100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz)
PHASE NOISE LOW-BAND OSCILLATOR vs. FREQUENCY OFFSET (130.38MHz)
MAX2360/2/4-13
PHASE NOISE HIGH-BAND OSCILLATOR vs. FREQUENCY OFFSET (165MHz)
MAX2360/2/4-14
RFL OUTPUT SPECTRUM
0 -10 AMPLITUDE (dBm) -20 -30 -40 -50 -60 -70 -80 DESIRED IMAGE LO
MAX2360/2/4-15
-50 -60 -70 -80 (dBc/Hz)
-50 -60 -70 -80 (dBc/Hz) -90 -100 -110 -120 -130 -140 -150
10
-90 -100 -110 -120 -130 -140 -150 1k 10k 100k FREQUENCY (Hz) 1M 10M
1k
10k
100k FREQUENCY (Hz)
1M
10M
-90 566.38 766.38 966.38 1166.38 1366.38 FREQUENCY (MHz)
RFH0 OUTPUT SPECTRUM
MAX2360/2/4-16
RFHO CASCADE ACPR vs. POUT AND VBAT
MAX2360/2/4-17
CASCADE ACPR vs. POUT AND VBAT
VCC = 2.75V 3.0V 2.8V 2.7V -55 -60 3.3V -65 3.6V -70 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 3.3V
MAX2360/2/4-18
10 0 -10 AMPLITUDE (dBm) -20
-40 -45 -50 ACPR (dBc)
VCC = 2.75V 3.0V 2.8V 2.7V
-40 -45 -50 ACPR (dBc)
-30 -40 -50 -60 -70 -80 -90 1350 1550 1750 1950 2150 FREQUENCY (MHz) IMAGE DESIRED LO
-55 -60 -65 3.6V -70 -10 -8 -6 -4 -2 0 2 4 6 POUT (dBm)
POUT (dBm)
6
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PARALLEL CAPACITANCE (pF)
Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
Typical Operating Characteristics (continued)
(MAX2360EVKIT, VCC = +2.75V, TA = +25C, unless otherwise noted.)
ICC vs. RFL OUTPUT POWER (836MHz)
MAX2360/2/4-19
ICC vs. RFH0 OUTPUT POWER (1880MHz)
MAX2360/2/4-21
ICC vs. RFH1 OUTPUT POWER (1880MHz)
170 160 ICC (mA) 150 140 130 120 110 100
MAX2360/2/4-21
180 170 160 ICC (mA)
180 170 160 ICC (mA) 150 140 130 120 110 100
180
150 140 130 120 110 100 -60 -50 -40 -30 -20 -10 0 10 OUTPUT POWER (dBm)
-60
-50
-40
-30
-20
-10
0
10
-60
-50
-40
-30
-20
-10
0
10
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
BUFFERED LO OUTPUT
MAX2360/2/4-22
LOL PORT S11
MAX2360/2/4-23
LOH PORT S11
MAX2360/2/4-24
0 -10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 129.18 129.78 130.38 130.98 131.58 FREQUENCY (MHz)
5 4 4 321 3 21
1: 2: 3: 4:
700MHz, 72 -j51 966MHz, 60 -j46 1.22MHz, 52 -j38 1.5GHz, 40 -j25
1600MHz TO 2500MHz 1: 1.6GHz, 40 -j25 2: 1.75GHz, 36 -j22 3: 1.88GHz, 34 -j18 4: 2.01GHz, 32 -j15 5: 2.5GHz, 29 -j0
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7
Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
Pin Description
PIN NAME MAX2360 MAX2362 MAX2364 Transmitter RF Output for Cellular Band (800MHz to 1000MHz)--for both FM and digital modes. This open-collector output requires a pull-up inductor to the supply voltage, which may be part of the output matching network and may be connected directly to the battery. FUNCTION
1
--
1
RFL
--
1, 8, 9, 18, 19, 30, 31, 34, 35, 44
2, 10, 11, 16, 17, 32-35 43, 47
N.C.
No Connection. Make no connection to these pins.
2
2
--
RFH0
Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This opencollector output requires a shunt inductor to the supply voltage. The pull-up inductor may be part of the output matching network and may be connected directly to the battery. Open-Collector Output Indicating Lock Status of the IF and/or the RF PLLs. Requires a pull-up resistor. Control using configuration register bit LD_MODEO, LD_MODE1. Power Supply Digital Input. A logic low on IDLE shuts down everything except the RF PLL and associated registers. A small RC lowpass filter may be used to prevent digital noise. Supply Pin for the Upconverter Stage. VCC must be bypassed to system ground as close to the pin as possible. The ground vias for the bypass capacitor should not be shared by any other branch. Digital Input. A logic low on TXGATE shuts down everything except the RF PLL, IF PLL, IF VCO, and serial bus and registers. This mode is used for gated transmission. Differential Inputs to the RF Upconverter. These pins are internally biased to 1.5V. The input impedance for these ports is nominally 400 differential. The IF filter should be AC-coupled to these ports. Keep the differential lines as short as possible to minimize stray pick-up and shunt capacitance. Differential Inputs to the RF Upconverter. These pins are internally biased to 1.5V. The input impedance for these ports is nominally 400 differential. The IF filter should be AC-coupled to these ports. Keep the differential lines as short as possible to minimize stray pick-up and shunt capacitance. Bias Resistor Pin. RBIAS is internally biased to a bandgap voltage of 1.18V. An external resistor or current source must be connected to this pin to set the bias current for the upconverters and PA driver stages. The nominal resistor value is 16k. This value can be altered to optimize the linearity of the driver stage. Input Pins from the 3-Wire Serial Bus (SPI/QSPI/MICROWIRE compatible). An RC filter on each of these pins may be used to reduce noise.
3 4
3 4
3 4
LOCK VCC IDLE
5
5
5
6
6
6
VCC
7
7
7
TXGATE
8, 9
--
8, 9
IFINL+, IFINL-
10, 11
10, 11
--
IFINH+, IFINH-
12
12
12
RBIAS
13, 14, 15
13, 14, 15
13, 14, 15
CLK, DI, CS
8
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Complete Dual-Band Quadrature Transmitters
Pin Description (continued)
PIN NAME MAX2360 MAX2362 MAX2364 Differential IF Outputs. These ports are active when the register bit IF_SEL is high. They do not support FM mode. These pins must be inductively pulled up to VCC. A differential IF bandpass filter is connected between this port and IFINH+ or IFINH-. The pull-up inductors can be part of the filter structure. The differential output impedance of this port is nominally 600. The transmission lines from these pins should be short to minimize the pick-up of spurious signals and noise. Differential IF Outputs. These ports are active when the register bit IF_SEL is low. These pins must be inductively pulled up to VCC. A differential IF bandpass filter is connected between this port and IFINL+ and IFINL-. The pull-up inductors can be part of the filter structure. The differential output impedance of this port is nominally 600. The transmission lines from these pins should be short to minimize the pick-up of spurious signals and noise. RF and IF Variable-Gain Control Analog Input. VGC floats to 1.5V. Apply 0.5V to 2.6V to control the gain of the RF and IF stages. An RC filter on this pin may be used to reduce DAC noise or PDM clock spurs from this line. Supply Pin for the IF VGA. Bypass with a capacitor as close to the pin as possible. The bypass capacitor must not share its ground vias with any other branches. Supply for the I/Q Modulator. Bypass with capacitor as close to the pin as possible. The bypass capacitor must not share its ground vias with any other branches. Differential Q-Channel Baseband Inputs to the Modulator. These pins go directly to the bases of a differential pair and require an external commonmode bias voltage. Differential I-Channel Baseband Inputs to the Modulator. These pins go directly to the bases of a differential pair and require an external commonmode bias voltage of 1.4V. Shutdown Input. A logic low on SHDN shuts down the entire IC. An RC lowpass filter may be used to reduce digital noise. Supply Pin to the VCO Section. Bypass as close to the pin as possible. The bypass capacitor should not share its vias with any other branches. Buffered LO Output. Control the output buffer using register bit BUF_EV and the divide ratio using the register bit BUF_DIV. Differential Tank Pins for the Low-Frequency IF VCO. These pins are internally biased to 1.6V. FUNCTION
MAX2360/MAX2362/MAX2364
16, 17
16, 17
--
IFOUTH-, IFOUTH+
18, 19
--
18, 19
IFOUTL+, IFOUTL-
20
20
20
VGC
21
21
21
VCC
22
22
22
VCC
23, 24
23, 24
23, 24
Q+, Q-
25, 26
25, 26
25, 26
I+, I-
27
27
27
SHDN
28
28
28
VCC
29
29
29
IFLO
30, 31
--
30, 31
TANKL-, TANKL+
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9
Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
Pin Description (continued)
PIN NAME MAX2360 32, 33 34, 35 MAX2362 32, 33 34, 35 MAX2364 -- 34, 35 TANKH-, TANKH+ N.C. Differential Tank Pins for the High-Frequency IF VCO. These pins are internally biased to 1.6V. No Connection. Leave these pins floating. Reference Frequency Input. REF is internally biased to VCC - 0.7V and must be AC-coupled to the reference source. This is a high-impedance port (25k II 3pF). Supply for the IF Charge Pump. This supply can differ from the system VCC. Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branches. High-Impedance Output of the IF Charge Pump. Connect to the tune input of the IF VCOs through the IF PLL loop filter. Keep the line from IFCP to the tune input as short as possible to prevent spurious pick-up, and connect the loop filter as close to the tune input as possible. Supply Pin for Digital Circuitry. Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branch. High-Impedance Output of the RF Charge Pump. Connect to the tune input of the RF VCOs through the RF PLL loop filter. Keep the line from this pin to the tune input as short as possible to prevent spurious pick-up, and connect the loop filter as close to the tune input as possible. Supply for the RF Charge Pump. This supply can differ from the system VCC. Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branches. RF PLL Input. AC-couple this port to the RF VCO. High-band RF LO Input Port. AC-couple to this port. Low-band RF LO Input Port. AC-couple to this port. Ground. Connect to PCB ground plane. Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This open-collector output requires a shunt inductor to the supply voltage. The pull-up inductor may be part of the output matching network and may be connected directly to the battery. DC and AC GND Return for the IC. Connect to PC board ground plane using multiple vias. FUNCTION
36
36
36
REF
37
37
37
VCC
38
38
38
IFCP
39
39
39
VCC
40
40
40
RFCP
41
41
41
VCC
42 43 44 45, 46, 48
42 43 -- 45, 46, 48
42 -- 44 45, 46, 48
RFPLL LOH LOL GND
47
47
--
RFH1
Exposed paddle
Exposed paddle
Exposed paddle
GND
10
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Complete Dual-Band Quadrature Transmitters
Detailed Description
The MAX2360 complete quadrature transmitter accepts differential I/Q baseband inputs with external commonmode bias. A modulator upconverts this to IF frequency in the 120MHz to 300MHz range. A gain control voltage pin (VGC) controls the gain of both the IF and RF VGAs simultaneously to achieve best noise and linearity performance. The IF signal is brought off-chip for filtering, then fed to a single sideband upconverter followed by the RF VGA and PA driver. The RF upconverter requires an external VCO for operation. The IF PLL, RF PLL, and operating mode can be programmed by an SPI/QSPI/ MICROWIRE-compatible 3-wire interface. The following sections describe each block in the MAX2360 Functional Diagram.
IFLO Output Buffer
IFLO provides a buffered LO output when BUF_EN is 1. The IFLO output frequency is equal to the VCO frequency when BUF_DIV is 0, and half the VCO frequency when BUF_DIV is 1. The output power is -6dBm. This output is intended for applications where the receive IF is the same frequency as the transmit IF.
MAX2360/MAX2362/MAX2364
IF/RF PLL
The IF/RF PLL uses a charge-pump output to drive a loop filter. The loop filter will typically be a passive second-order lead lag filter. Outside the filter's bandwidth, phase noise will be determined by the tank components. The two components that contribute most significantly to phase noise are the inductor and varactor. Use high-Q inductors and varactors to maximize equivalent parallel resistance. The IF_TURBO_CHARGE and the RF_TURBO_CHARGE bits in the CONFIG register can be set to 1 to enable turbo mode. Turbo mode provides maximum charge-pump current during frequency acquisition. Turbo mode is disabled after the second transition from phase lead to phase lag or from phase lag to phase lead. Turbo mode is also disabled after frequency acquisition is achieved. When turbo mode is disabled, charge-pump current will return to the programmed levels as set by ICP and RCP bits in the CONFIG register (Table 4).
I/Q Modulator
Differential in-phase (I) and quadrature-phase (Q) input pins are designed to be DC-coupled and biased with the baseband output from a digital-to-analog converter (DAC). I and Q inputs need a DC bias of VCC/2 and a current-drive capability of 6A. Common-mode voltage will work within a +1.35V to (V CC - 1.25V) range. Typically, I and Q will be driven differentially with a 200mVRMS baseband signal. Optionally, I and Q may be programmed for 100mVRMS operation with the IQ_LEVEL bit in the configuration register. The IF VCO output is fed into a divide-by-two/quadrature generator block to derive quadrature components to drive the IQ modulator. The output of the modulator is fed into the VGA.
IF VGA
The IF VGA allows varying an IF output level that is controlled by the VGC. The voltage range on VGC of 0.5V to 2.6V. provide a gain-control range of 85dB. There are two differential IF output ports from the VGA. IFOUTL+/IFOUTL- are optimized for low IF operation (120MHz to 235MHz) for IFOUTH+/IFOUTH- support high IF operation (120MHz to 300MHz). IFOUTL ports support direct VCO FM modulation. The differential IF output port has an output impedance of 600 when pulled up to VCC through a choke.
IF VCOs
There are two VCOs to support high IF and low IF applications. The VCOs oscillate at twice the desired IF frequency. Oscillation frequency is determined by external tank components (see Applications Information). Typical phase-noise performance for the tank is as shown in Table 1. The high-band and low-band VCOs can be selected independently of the IF port being used.
Single Sideband Mixer
The RF transmit mixer uses a single sideband architecture to eliminate an off-chip RF filter. The single sideband mixer has IF input stages that correspond to IF output ports of the VGA. The mixer is followed by the RF VGA. The RF VGA is controlled by the same VGC pin as the IF VGA to provide optimum linearity and noise performance. The total power control range is >100dB.
Table 1. Typical VCO Phase Noise (IF = 130.38MHz)
OFFSET (kHz) 1 12.5 30 120 900 PHASE NOISE (dBc) -80 -105 -111 -121 -128
PA Driver
The MAX2360 includes three power-amplifier (PA) drivers. Each is optimized for the desired operating frequency. RFL is optimized for cellular-band operation.
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Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
RFH0 and RFH1 are optimized for split-band PCS operation. The PA drivers have open-collector outputs and require pull-up inductors. The pull-up inductors can act as the shunt element in a shunt series match. The configuration register (CONFIG) sets the configuration for the RF/IF PLL and the baseband I/Q input levels. See Table 4 for a description of each bit. The test register is not needed for normal use. Power Management Bias control is distributed among several functional sections and can be controlled to accommodate many different power-down modes as shown in Table 5. The shutdown control bit is of particular interest since it differs from the SHDN pin. When the shutdown control bit is active (SHDN_BIT = 0), the serial interface is left active so that the part can be turned on with the serial bus while all other functions remain shut off. In contrast, when the SHDN pin is low it shuts down everything. In either case, PLL programming and register information is lost. To retain the register information, use standby mode (STBY = 0). Signal Flow Control Table 6 shows an example of key registers for triplemode operation, assuming half-band PCS and IF frequencies of 130MHz/165MHz.
Programmable Registers
The MAX2360/MAX2362/MAX2364 include seven programmable registers consisting of four divide registers, a configuration register, an operational control register, and a test register. Each register consists of 24 bits. The 4 least significant bits (LSBs) are the register's address. The 20 most significant bits (MSBs) are used for register data. All registers contain some "don't care" bits. These can be either a "0" or a "1" and will not affect operation (Figure 1). Data is shifted in MSB first, followed by the 4-bit address. When CS is low, the clock is active and data is shifted with the rising edge of the clock. When CS transitions to high, the shift register is latched into the register selected by the contents of the address bits. Power-up defaults for the seven registers are shown in Table 2. The dividers and control registers are programmed from the SPI/ QSPI/MICROWIRE-compatible serial port. The RFM register sets the main frequency divide ratio for the RF PLL. The RFR register sets the reference frequency divide ratio. The RF VCO frequency can be determined by the following: RF VCO frequency = fREF * (RFM / RFR) IFM and IFR registers are similar: IF VCO frequency = fREF * (IFM / IFR) where fREF is the external reference frequency for the MAX2360/MAX2362/MAX2364. The operational control register (OPCTRL) controls the state of the MAX2360/MAX2362/MAX2364. See Table 3 for the function of each bit.
Applications Information
The MAX2360 is designed for use in dual-band, triplemode systems. It is recommended for triple-mode handsets (Figure 2). The MAX2362 is designed for use in CDMA PCS handset or WLL single-mode 2.4GHz ISM systems (Figure 3). The MAX2364 is designed for use in dual-mode cellular systems (Figure 4).
3-Wire Interface
Figure 5 shows the 3-wire interface timing diagram. The 3-wire bus is SPI/QSPI/MICROWIRE compatible.
Table 2. Register Power-Up Default States
REGISTER RFM RFR IFM IFR OPCTRL CONFIG TEST DEFAULT 172087 dec 1968 dec 6519 dec 0492 dec 892F hex D03F hex 0000 hex ADDRESS 0000b 0001b 0010b 0011b 0100b 0101b 0111b RF M divider count RF R divider count IF M divider count IF R divider count Operational control settings Configuration and setup control Test-mode control FUNCTION
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Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
MSB 24 BIT REGISTER DATA 20 BITS LSB ADDRESS 4 BITS
B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A3 A2 A1 A0 RFM DIVIDE RATIO (18) X X B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 RFR DIVIDE RATIO (13) X X X X X X X B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 IFM DIVIDE RATIO (14) X X X X X X B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 RFR DIVIDE RATIO (11) X X X X X X X X X B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONTROL BITS (16) X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONFIGURATION BITS (16) X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 ADDRESS 0 0 0
RFM DIVIDE REGISTER
RFR DIVIDE REGISTER
ADDRESS 0 0 1
IFM DIVIDE REGISTER
ADDRESS 0 1 0
IFR DIVIDE REGISTER
ADDRESS 0 1 1
CONTROL REGISTER
ADDRESS 1 0 0
CONFIGURATION REGISTER
ADDRESS 1 0 1
TEST REGISTER
TEST BITS (8) X X X X X X X X X X X X B7 B6 B5 B4 B3 B2 B1 B0 0
ADDRESS 1 1 1
X = DON'T CARE
Figure 1. Register Configuration
Electromagnetic Compliance Considerations
Two major concepts should be employed to produce a noise-free and EMC-compliant transmitter: minimize circular current-loop area to reduce H-field radiation and minimize voltage drops to reduce E-field radiation. To minimize circular current-loop area, bypass as close to the part as possible and use the distributed capacitance of a ground plane. To minimize voltage drops, make VCC traces short and wide, and make RF traces short. The "don't care" bits in the registers should be "0" in order to minimize electromagnetic radiation due to unnecessary bit banging. RC filtering can also be used to slow the clock edges on the 3-wire interface, reducing high-frequency spectral content. RC filtering also
provides for transient protection against IEC802 testing by shunting high frequencies to ground, while the series resistance attenuates the transients for error-free operation. The same applies to the override pins (SHDN, TXGATE, IDLE). High-frequency bypass capacitors are required close to the pins with a dedicated via to ground. The 48-pin TQFP-EP package provides minimal inductance ground by using an exposed paddle under the part. Provide at least five low-inductance vias under the paddle to ground, to minimize ground inductance. Use a solid ground plane wherever possible. Any cutout in the ground plane may act as slot radiator and reduce its shield effectiveness. Keep the RF LO traces as short as possible to reduce LO radiation and susceptibility to interference.
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Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
Table 3. Operation Control Register (OPCTRL)
BIT NAME LO_SEL POWER-UP STATE 1 BIT LOCATION (0 = LSB) 15 FUNCTION 1 selects LOL input port; 0 selects LOH port. 1 keeps RF turbo-mode current active even when frequency acquisition is achieved. This bit has no effect when RF_TURBO_CHARGE = 0. This mode is used when high operating RF charge-pump current is needed. 1 keeps IF turbo-mode current active even when frequency acquisition is achieved. This bit has no effect when IF_TURBO_CHARGE = 0. This mode is used when high operating IF charge-pump current is needed. Sets operating mode according to the following: 00 = FM mode 01 = Cellular digital mode, RFL is selected 10 = PCSHIGH mode, RFH1 is selected 11 = PCSLOW mode, RFH0 is selected 1 selects IFINH and IFOUTH; 0 selects IFINL and IFOUTL. For FM mode (MODE = 00), set IF_BAND to 0. 1 selects high-band IF VCO; 0 selects low-band IF VCO. 3-bit IF gain control. Alters IF gain by approximately 2dB per LSB (0 to 14dB). Provides a means for adjusting balance between RF and IF gain for optimized linearity. When this register is 1, the upper sideband is selected (LO below RF). When this register is 0, the lower sideband is selected (LO above RF). 0 turns IFLO buffer off; 1 turns IFLO buffer on. 0 selects direct VCO modulation. (IF VCO is externally modulated and the I/Q modulator is bypassed); 1 selects quadrature modulation. 0 shuts down everything except registers and serial interface. 0 shuts down modulator and upconverter, leaving PLLs locked and registers active. This is the programmable equivalent to the TXGATE pin. 0 shuts down everything except serial interface, and also resets all registers to power-up state.
RCP_MAX
0
14
ICP_MAX
0
13
MODE
01
12, 11
IF_BAND VCO
0 0
10 9
IFG
100
8, 7, 6
SIDE_BAND BUF_EN MOD_TYPE STBY TXSTBY
1 0 1 1 1
5 4 3 2 1
SHDN_BIT
1
0
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Complete Dual-Band Quadrature Transmitters
Table 4. Configuration Register (CONFIG)
BIT NAME IF_PLL_SHDN RF_PLL_ SHDN RESERVED IQ_LEVEL BUF_DIV VCO_BYPASS POWER-UP STATE 1 1 0 1 0 0 BIT LOCATION (0 = LSB) 15 14 13 12 11 10 FUNCTION 0 shuts down the IF PLL. This mode is used with an external IF VCO and IF PLL. 0 shuts down the BF PLL. This mode is used with an external RF PLL. Must be set to 0 for normal operation. 1 selects 200mVRMS input mode; 0 selects 100mVRMS input mode. 1 selects /2 on IFLO port; 0 bypasses the divider. 1 bypasses IF VCO and enables a buffered input for external VCO use. A 2-bit register sets the IF charge-pump current as follows: 00 = 175A 01 = 235A 10 = 350A 11 = 465A A 2-bit register sets the RF charge-pump current as follows: 00 = 165A 01 = 230A 10 = 340A 11 = 450A IF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage on the VCO produces increasing frequency); 0 selects negative polarity (increasing tuning voltage on the VCO produces decreasing frequency). RF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage on the VCO produces increasing frequency); 0 selects negative polarity (increasing voltage on the VCO produces decreasing frequency). 1 activates turbocharge feature, providing an additional 450A of IF chargepump current during frequency acquisition. 1 activates turbocharge feature, providing an additional 435A of IF chargepump current during frequency acquisition. Determines output mode for LOCK detector pin as follows: 00 = test mode, LD_MODE cannot be 00 for normal operation 01 = IF PLL lock detector 10 = RF PLL lock detector 11 = logical AND of IF PLL and RF PLL lock detectors
MAX2360/MAX2362/MAX2364
ICP
00
9, 8
RCP
00
7, 6
IF_PD_POL
1
5
RF_PD_POL
1
4
IF_TURBO_ CHARGE RF_TURBO_ CHARGE
1
3
1
2
LD_MODE
11
1, 0
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Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
Table 5. Power-Down Modes
UPCONVERTER RF PLL REGS OPCTRL REG MODULATOR CONFIG REG X X IF PLL REGS X X X X H H H H H H H H L SHDN SERIAL BUS IF LO BUFF
RF PLL
IF VCO X X X X H H H H L L H H X IDLE
POWER-DOWN MODE
COMMENTS
SHDN Pin IDLE Pin TXGATE pin RF PLL SHDN IF PLL SHDN TX STBY REG STBY REG SHDN X = Off
Ultra-low shutdown current IDLE is low in RX mode For punctured TX mode For external RF PLL use For external IF PLL use TX is OFF, but IF and RF LOs stay locked Shuts down, but preserves registers Serial bus is still active
X X X
X X X
X
X
X
X
X X
X X X X X X X X X
X X X X X X X X
Table 6. Register and Control Pin States for Key Operating Modes
OPCTRL REGISTER CONFIG REGISTER CONTROL PINS
FM TYPE
PCS High PCS Low Cellular Digital FM PCS Idle Cellular Idle PCS TXGATE Cellular TXGATE Sleep X = Don't care
PCS upper half-band, RFH1 selected PCS lower half-band, RFH0 selected RFL selected Direct VCO modulation, RFL selected Listen for pages RX ON, TX OFF Listen for pages RX ON, TX OFF Gated transmission, PCS Gated transmission, cellular digital Everything off
0 0 1 1 0 1 0 1 X
10 11 01 00 1X 0X 1X 01 XX
1 1 0 0 X X 1 0 X
1 1 0 0 X X 1 0 X
1 1 1 0 X X 1 1 X
1 1 1 1 1 1 1 1 X
1 1 1 1 X X X X X
1 1 1 1 1 1 1 1 X
1 1 1 1 X X 1 1 X
1 1 1 1 1 1 1 1 X
H H H H H H L L X
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TXGATE
IF BAND
TXSTBY
LO SEL
MODE
STBY
MODE
DESCRIPTION
RF PLL SHDN
IF PLL SHDN
SHDN_BIT
VCO
IF PLL X X
VREG VBAT 100pF 3300pF 0.033F CELL VCO 5nH 1880MHz 33pF 50 33pF 33pF
PCS PA
VBAT 100pF 100pF PCS VCO
PCS Rx 1960MHz 22nH VBAT 10k 33pF
PCS DUPLEXER 3.3pF 8.7H 48 3300pF 0.033F 36 35 N.C. IF PPL 3 100pF 4 VCC 90 0 6 VCC TANK L 32 5 33 22nH TANK H 4.3pF 12pF 10k 18pF 10k 34 N.C. 12pF 19.68MHz TCXO 10k 3pF VCC 1 836MHz VREG 2 51k RF PPL
CELL PA
CELL RX
47
46
45
44
43
42
41
40
39
38
37
0.033F
165MHz
DAC
Figure 2. MAX2360 Typical Application Circuit
10k
DIPLEXER
CELL DUPLEXER
LOCK
IDLE
VREG
MAX2360
45 /2 -45
31 30 29 IFLO 28 27 SHDN 90 /2 26 DAC I 25 39nH 2.4pF
1000pF 7 8 9 10 11 12 RBIAS 16k 13 14 15 16 17 18 CLK DI CS 19 VGC 20 21 VCC 22 23 24 0
TXGATE
18pF
10k VREG 100pF
130MHz
DAC
Q
VREG
MAX2360/MAX2362/MAX2364
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3 WIRE 100pF 100pF
Complete Dual-Band Quadrature Transmitters
17
MAX2360/MAX2362/MAX2364
PCS DUPLEXER 1880MHz 33pF 33pF 3.3pF N.C. 48 3300pF 0.033F 36 35 N.C. IF PLL 3 100pF 4 VCC 90 0 6 VCC 32 5 33 TANK 39nH 2.4pF 18pF 10k 34 N.C. 19.68MHz TCXO 18pF 10k VCC 1 N.C. RF PLL VREG 2 47 46 45 44 43 42 41 40 39 38 37 VCC 0.033F 33pF 10k
Complete Dual-Band Quadrature Transmitters
Figure 3. MAX2362 Typical Application Circuit
PCS PA
0.033F
5nH
3300pF
DAC
18
VBAT 100pF 100pF VREG 100pF VBAT PCS VCO 22nH 10k
PCS Rx 1960MHz
51k
LOCK
IDLE
VREG
MAX2362
45 /2 -45
31 N.C. 30 N.C. 29 IFLO 28 27 SHDN VREG 100pF /2 90 26 DAC I 25
1000pF 7 47pF N.C. 8 N.C. 9 10 11 12 RBIAS 16k 13 14 15 16 17 CLK 18 N.C. DI CS 19 N.C. VGC 20 21 VCC 22 23 0
TXGATE
130MHz
24 DAC Q
______________________________________________________________________________________
VREG 3 WIRE 100pF 100pF
PCS VCO 100pF 100pF VREG 3300pF 0.033F 100pF
CELL Rx 880MHz VBAT 10k 33pF N.C. N.C. 46 3300pF 0.033F 1 836MHz VREG IF PLL 3 100pF 4 VCC 5 0 TANK L VCC 6 90 32 N.C. 18pF 31 30 /2 29 IFLO 28 27 N.C. 11 12 RBIAS 16k 13 N.C. N.C. DAC DAC Q 14 15 16 17 18 CLK DI CS 19 VGC 20 21 VCC 22 23 24 0 90 /2 26 DAC 25 I SHDN 39nH 2.4pF 18pF 10k VREG 100pF 10k 33 N.C. 34 N.C. N.C. 2 35 N.C. RF PLL 36 19.68MHz TCXO 10k 45 44 43 42 41 40 39 38 37 0.033F 48 47 33pF
CELL DUPLEXER 8.7nH 3pF
Figure 4. MAX2364 Typical Application Circuit
MAX2364
45 7 47pF 8 9 N.C. 10 -45 VREG 3 WIRE 100pF 100pF
CELL PA
51k
LOCK
IDLE
VREG
1000pF
TXGATE
MAX2360/MAX2362/MAX2364
______________________________________________________________________________________
130MHz
Complete Dual-Band Quadrature Transmitters
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Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
DI B19 (MSB) B18 B0 A3 A1 A0 (LSB) tCS > 50ns tCH > 10ns tCWH > 50ns tES > 50ns tCWL > 50ns tEW > 50ns tEW
CLK tCWL tCS CS tCH tCWH tES
Figure 5. 3-Wire Interface Diagram
IF Tank Design
The low-band tank (TANKL+, TANKL-) and high-band tank (TANKH+, TANKH-) are fully differential. The external tank components are shown in Figure 6. The frequency of oscillation is determined by the following equation: 1 fOSC = 2 (CINT + CCENT + CVAR + CP CVAR = CD x CC 2 (CD + CC )
CC
CD CCENT CD L CPAR CINT
MAX2360 MAX2362 MAX2364
-Rn
CC
CINT = Internal capacitance of TANK port CD = Capacitance of varactor CVAR = Equivalent variable tuning capacitance CPAR = Parasitic capacitance due to PCB pads and traces CCENT = External capacitor for centering oscillation frequency CC = External coupling capacitor to the varactor Internal to the IC, the charge pump will have a leakage of less than 10nA. This is equivalent to a 300M shunt resistor. The charge-pump output must see an extremely high DC resistance of greater than 300M. This will minimize charge-pump spurs at the comparison frequency. Make sure there is no solder flux under the varactor or loop filter.
Figure 6. Tank Port Oscillator
Power-Supply Layout
To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central VCC node. The VCC traces branch out from this node, each going to a separate VCC node in the MAX2360/ MAX2362/MAX2364 circuit. At the end of each trace is a bypass capacitor with impedance to ground less than 1 at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection.
Layout Issues
The MAX2360/MAX2362/MAX2364 EV kit can be used as a starting point for layout. For best performance, take into consideration power-supply issues as well as the RF, LO, and IF layout.
Matching Network Layout
The layout of a matching network can be very sensitive to parasitic circuit elements. To minimize parasitic inductance, keep all traces short and place components as close to the IC as possible. To minimize parasitic capacitance, a cutout in the ground plane (and
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Complete Dual-Band Quadrature Transmitters
any other planes) below the matching network components can be used. On the high-impedance ports (e.g., IF inputs and outputs), keep traces short to minimize shunt capacitance.
Tank Layout
Keep the traces coming out of the tank short to reduce series inductance and shunt capacitance. Keep the inductor pads and coupling capacitor pads small to minimize stray shunt capacitance.
MAX2360/MAX2362/MAX2364
Selector Guide
PART MAX2360 MAX2362 MAX2364 IF RANGE (MHz) 120 to 235 120 to 300 120 to 300 120 to 235 RF LO RANGE (MHz) 800 to 1150 1400 to 2300 1400 to 2300 800 to 1150 RF RANGE (MHz) 800 to 1000 1700 to 2000 1700 to 2000 800 to 1000
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Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
Pin Configurations (continued)
TOP VIEW
LOH RFPLL VCC GND RFH1 GND GND N.C. LOH RFPLL VCC RFCP VCC IFCP VCC
48 47 46 45 44 43 42 41 40 39 38
RFCP VCC
40 39
GND RFH1 GND
48
47
46
45
44
43
42
41
38
37
IFCP VCC
GND LOL
RFL RFH0 LOCK VCC IDLE VCC TXGATE IFINL+ IFINLIFINH+ IFINHRBIAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
REF N.C. N.C. TANK H+ TANKHTANKL+ TANKLIFLO VCC SHDN II+
37
N.C. RFH0 LOCK VCC IDLE VCC TXGATE N.C. N.C. IFINH+ IFINHRBIAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
REF N.C. N.C. TANKH+ TANKHN.C. N.C. IFLO VCC SHDN II+
MAX2360
MAX2362
CLK DI CS IFOUTHIFOUTH+ IFOUTL+
IFOUTLVGC VCC
VCC Q+ Q-
CLK DI CS IFOUTHIFOUTH+ N.C. N.C. VGC VCC VCC
TQFP-EP
GND N.C. GND GND LOL N.C. RFPLL VCC RFCP VCC IFCP VCC
TQFP-EP
48
47
46
45
44
43
42
41
40
39
38
37
RFL N.C. LOCK VCC IDLE VCC TXGATE IFINL+ IFINLN.C. N.C. RBIAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
MAX2364
REF N.C. N.C. N.C. N.C. TANKL+ TANKLIFLO VCC SHDN II+
CLK DI CS N.C. N.C. IFOUTL+ IFOUTLVGC VCC VCC
BOTTOM SIDE GND
TQFP-EP
22
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Q+ Q-
Q+ Q-
Complete Dual-Band Quadrature Transmitters
Package Information
48L,TQFP.EPS
MAX2360/MAX2362/MAX2364
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Complete Dual-Band Quadrature Transmitters MAX2360/MAX2362/MAX2364
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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